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Experienced and versatile electronics engineer with an all round experience in digital electronics. Very flexible, and always willing to learn and expand my skills.
I started my career working on micro-processor design, multi-core designs and multimedia hardware acceleration, as well as on chip layout (from synthesis to GDS2 delivery). In more recent times I have worked on FPGA prototyping, focusing on scalable multi-FPGA platforms for verification as well as software prototyping.
I have worked both in EDA companies (Cadence Design Systems, and Mentor Graphics – A Siemens Business), as well as in IP design companies (e.g. ARC International, ARM) as a user of EDA tools, and I have been involved not only in design and architecture, but also in methodology development and re-use.
Mentor Graphics – A Siemens Business (2016 – present)
Building on the experience acquired while working on FPGA platforms for verification and prototyping at ARM, I joined Mentor Graphics – A Siemens Business at the start of 2016, to work on the architecture, design and development of a multi-FPGA platform targeted to prototyping and debug. I have been instrumental in developing and successfully delivering a system level model for this multi-FPGA platform and a flow associated with it, to enable the prototyping of associated software and IP ahead of hardware availability, and to provide a simulation platform methodology accompanying the tool flow. The system level model was made available to internal as well as external
stakeholders, and enabled accelerated hardware bring up.
Project Highlights at Mentor
- Multi-FPGA Prototyping Platform
Architecture, design, modelling, and methodology.
ARM Ltd – (2012 – 2016)
At the start of 2012 I began working at ARM Ltd, the world leader in semiconductor intellectual property (IP) supplier. I am part of a group which takes IP designs from all parts of the organization, in order to build systems for verification, software prototyping and, not least, reference standards development.
My role in the group is to be in charge of the FPGA development for the group, and link between the various stakeholders with interests in the FPGA platforms implementing the group’s designs.
Since joining I have been involved in the latest leading edge technology FPGA platforms, implementing the largest and newest FPGA part from one of the world leading FPGA suppliers. This meant working closely with the supplier, the other FPGA teams in ARM, and leveraging this experience in helping define the next FPGA platform, and driving requirements into the FPGA suppliers.
Project Highlights at ARM
- Virtex-7 based platform development
I was the first person in ARM to pick up the work for the then new multi-FPGA Virtex-7 2000T based platform, and worked closely with the FGPA supplier on early access silicon and tools to develop the flow, iron out issues, and get designs working on it.
- PCI-Express implementation
I was responsible for porting to the FGPA platform the PCI-Express macro, and this proved an interesting challenge due to various logic and silicon related bugs. I had to closely work with software and RTL engineers to debug and fix the issues.
- v8 GPU platform development
I was responsible for integrating the ARM GPU into a v8 architecture (64-bit) based build, and deliver it to our software teams in time for a keynote demo at the APM (ARM Partner Meeting).
Link Research Ltd – Vislink (2009 – 2011)
In this period I was employed as an FPGA Design Engineer at Vislink. I was involved in various Virtex-5 based designs and was heavily instrumental in developing the new MicroBlaze-based processor platforms for current and future products, and took responsibility for introducing a revision control system, coupled with a new design flow.
Project Highlights at Link Research – Vislink
- MicroBlaze platform development
I quickly became one of the few experts in the R&D department on Xilinx MicroBlaze implementation, as its adoption coincided with my joining the company, and I have become the first port of call for any MicroBlaze related issues.
- Ported diversity design from Virtex-2 to Virtex-5
This involved adapting existing code to the new FPGA platform, including the use of on-chip Rocket-IOs, unavailable for older FPGAs.
- IP Encapsulation/De-Encapsulation on Transport Stream
This involved converting an Ethernet-IPv4 input to an ASI transport stream output, and then converting it back at the other end to the original Ethernet-IPv4 stream.
- Revision Control System introduction – Design flow re-design
Strong of my experience in previous jobs, I realized the need for the introduction of a revision control system, and a structure for re-usable IP. I therefore took on the job of setting up and rolling out a Subversion based repository, and, together with a colleague, developed a new design flow to make the most of the new repository and associated IP structure.
ARC International (2005 – 2009)
During my time at ARC, I have been involved in various projects across the whole ARC Processor and Subsystem families, and in the development of the first ARC multi-core solution, AM 401V. I have also had the responsibility of managing the release of the ARC Video Variants (HW and SW), which was successfully delivered on schedule.
Project Highlights at ARC International
- Development of the first ARC Multi-Core Audio/Video Solution
Completed top-level system integration, creating a multi-core audio/video media player solution. This involved connecting two processor cores and a media processor to a shared fabric to produce a complete solution. I developed and integrated RTL, and performed synthesis and P&R benchmarking in various technologies (130nm to 65nm).
- Managing the ARC Video Variant Release
Achieved the ahead-of-schedule release of four new products in the ARC Advanced Video product line. Managed of a small team of HW and SW engineer, coordinated with other teams (e.g. Tools, TechPubs, Verification, etc.), supervised software testing and participated in integration work.
- Benchmarking Activity
Enhanced the existing of Power benchmarking flow and methodology, and produced various post-layout power, area and speed benchmarks.
- Motion Estimation module design for Video Subsystem
Architecture Design and Specification, RTL design, IP Library integration, verification.
- ARC 600 and ARC 700 processor maintenance
Involved in maintenance work for the ARC 600 and ARC 700 family products. This included integration, RTL, and test work.
- Methodology work
Worked on various quality process and methodology improvement and enhancements, e.g. redefining methodology for allocating auxiliary space across all the ARC processor families.
Cadence Design Systems (2000 – 2005)
I started off in Cadence Design Systems in Scotland as a chip layout engineer, and as such I was exposed to all stages of the design cycle, from synthesis, STA, Place and Route, to GDSII delivery, before moving into front-end design and verification.
Project Highlights at Cadence Design Systems
- PLB to PCI Bridge SystemC model implementation
Designed bridge master and slave interfaces to PLB bus (with inbound and outbound write buffers management and split transaction support), and bridge configuration module with relative interface, for use by customer verification team.
- SystemC based verification methodology development
Implemented templates and template-based verification components on Cadence Incisive methodology development project, using actual customer design as DUT. Verification components included transactors and monitors. Implemented tests and run script environment.
- PCI-Express IP development
Implemented Transaction Layer functionality. Verified Transaction, Data-Link and Physical layer functionality, developing transactor based verification environment.
- RTL Compiler new version evaluation
Enabled USA R&D group to meet deadline by leveraging access to actual complex customer designs to put through their new flagship tool. Evaluated synthesis results by comparing with post P&R results, using different flows and designs. Tested and debugged tool internal flow. Worked in USA site for about 1.5 months.
- Switch fabric chip
Worked on various module and top-level aspects of largest chip layout undertaken by the company until then. The final chip was about 18mmX18mm in size, contained over 132 RAMs, and 12M+ gates, running at a system core frequency of 200+MHz. Activities undertaken include module layout (from synthesis to GDSII), top-level power routing, pad placement and manual clock balancing, as the automatic tool couldn’t meet the stringent clock skew constraints.
- TV Set top box chip
Validated constraints for various modules, and taken them from RTL to GDSII (including STA, P&R, formal and physical verification), at 0.18um technology.
- Technology porting of a web cam graphics chip
Ported chip layout from 0.25um to 0.18um technology, by taking design modules through full P&R flow (including STA, formal and physical verification).
Other work experience
- Degree thesis works
Architected and implemented a microcontroller for embedded applications, on a joint project with ST-Microelectronics. This was a scalable microcontroller (8-16 bits), with basic MMU, using a 3-stage pipeline, with extra stages for more complex instructions.
- Volunteer Work (over the years):
While a student I often worked over the years as a volunteer for Ligue pour la Lecture de la Bible (Scripture Union) in Lausanne, Switzerland.
For a period of several years I was part of a volunteer organization providing emergency and non-emergency ambulance service to the local area of the city where I lived.
- MSc Degree in Electronics Engineering with top grades. Thesis title: “Design and implementation a scalable RISC processor”. The thesis work was carried out in cooperation with ST-Microelectronics.
- University Exchange Program Erasmus in the Netherlands.
- Operating Systems: Windows, UNIX, Linux, MAC OS.
- Languages: C, C++, Assembler, SystemC, csh, perl, tcl, php
- Hardware description languages: VHDL, Verilog
- Simulation tools: Modelsim, NCSim, Incisive, VCS
- ASIC Synthesis tools: Synopsys, Cadence
- Formal verification tools: Cadence Conformal
- P&R tools: Cadence
- Timing Analysis tools: Cadence Pearl, Cadence Encounter, Synopsys PrimeTime, Xilinx Vivado
- Physical Verification tools: Mentor Calibre, Cadence Virtuoso DFII editor
- FPGA design tools: Synopsys Synplify, Xilinx ISE, Xilinx Vivado, Mentor Precision, Mentor VPS
- Mathematical programs: Matlab
- IP Configuration Tool: ARChitect2
- Italian: mother tongue
- English: excellent
- French: excellent
I volunteer regularly in my local church, where I am an active member.
I volunteer with a charity that runs canal boats, aimed mainly (but not only) at people with disabilities.
I like tinkering with PCs and related hardware, often to the advantage of family and friends!
I am quite fond of classical music, although not an expert, and I always enjoy a good concert or opera, and I can spend quite a lot of time reading books, which is something I never stopped doing since I learned: more or less all genres, with the exception of horror.
Available on request.